| dc.contributor.author | Baer, Jean-Loup | en_US |
| dc.date.accessioned | 2016-04-08T08:00:50Z | |
| dc.date.available | 2016-04-08T08:00:50Z | |
| dc.date.issued | 2010 | en_US |
| dc.identifier.isbn | 978-0-511-67546-1 | en_US |
| dc.identifier.isbn | 978-0-521-76992-1 | en_US |
| dc.identifier.uri | https://lib.hpu.edu.vn/handle/123456789/20798 | |
| dc.description.abstract | This book has three main parts. Chapter 1 and Chapter 2 review material that should have been taught in a prerequisite class. Chapters 3 through 6 describe single-processor systems and their memory hierarchy. Chapter 7 and Chapter 8 are devoted to parallelism. The last (short) chapter, Chapter 9, introduces limitations due to technology and presents challenges for future CMPs. | en_US |
| dc.format.extent | 384 p. | en_US |
| dc.format.mimetype | application/pdf | |
| dc.language.iso | en | en_US |
| dc.publisher | Cambridge University Press | en_US |
| dc.subject | Microprocessor architecture | en_US |
| dc.subject | Chip multiprocessors | en_US |
| dc.subject | Electronic | en_US |
| dc.title | Microprocessor Architecture: From Simple Pipelines to Chip Multiprocessors | en_US |
| dc.type | Book | en_US |
| dc.size | 12.33 MB | en_US |
| dc.department | English resources | en_US |
