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dc.contributor.authorYu, Haoen_US
dc.contributor.authorWang, Yuhaoen_US
dc.date.accessioned2018-03-20T07:28:11Z
dc.date.available2018-03-20T07:28:11Z
dc.date.issued2014en_US
dc.identifier.isbn978-1-4939-0550-8en_US
dc.identifier.isbn978-1-4939-0551-5en_US
dc.identifier.otherHPU1160585en_US
dc.identifier.urihttps://lib.hpu.edu.vn/handle/123456789/29832
dc.description.abstractThis book presents the latest techniques for characterization, modeling and design for nano-scale non-volatile memory (NVM) devices. Coverage focuses on fundamental NVM device fabrication and characterization, internal state identification of memristic dynamics with physics modeling, NVM circuit design and hybrid NVM memory system design-space optimization. The authors discuss design methodologies for nano-scale NVM devices from a circuits/systems perspective, including the general foundations for the fundamental memristic dynamics in NVM devices. Coverage includes physical modeling, as well as the development of a platform to explore novel hybrid CMOS and NVM circuit and system design. Offers readers a systematic and comprehensive treatment of emerging nano-scale non-volatile memory (NVM) devices. Focuses on the internal state of NVM memristic dynamics, novel NVM readout and memory cell circuit design and hybrid NVM memory system optimization. Provides both theoretical analysis and practical examples to illustrate design methodologies. Illustrates design and analysis for recent developments in spin-toque-transfer, domain-wall racetrack and memristors.en_US
dc.format.extent200 p.en_US
dc.format.mimetypeapplication/pdfen_US
dc.language.isoenen_US
dc.publisherSpringer-Verlag New Yorken_US
dc.subjectEmerging nano-scaleen_US
dc.subjectNon-volatile memoryen_US
dc.subjectNanoen_US
dc.subjectElectronics and microelectronicsen_US
dc.titleDesign Exploration of Emerging Nano-scale Non-volatile Memoryen_US
dc.typeBooken_US
dc.size8,692 KBen_US
dc.departmentTechnologyen_US


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