Please use this identifier to cite or link to this item: https://lib.hpu.edu.vn/handle/123456789/24900
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dc.contributor.authorYu, Taoen_US
dc.date.accessioned2017-06-08T09:39:47Z
dc.date.available2017-06-08T09:39:47Z
dc.date.issued2016en_US
dc.identifier.otherHPU4160742en_US
dc.identifier.urihttps://lib.hpu.edu.vn/handle/123456789/24900en_US
dc.description.abstractThe Tunnel-FET (TFET), where carrier injection is determined by gate-controlled tunneling from the source to the channel, has been attractive as one of the promising candidates for future ultra-low power applications. In this thesis, inline-TFETs with tunneling direction aligned to the gate electric field are designed, fabricated and analyzed based on InGaAs/GaAsSb material. Using ultrathin InGaAs/GaAsSb quantum-well (QW), the device fabrication technology was developed and the tunneling properties of two successive generations of QWTFETs were investigated. In the first generation QWTFETs, the limitation of gate oxide quality on InGaAs and parasitic thermal currents manifests itself in degraded subthreshold swing (SS) of 140 mV/dec, as well as strongly temperature dependent SS from 300 K to 77 K. The second generation QWTFETs with sub-nm InP cap between gate oxide and InGaAs channel and revised structure design has demonstrated improved SS of 87 mV/dec at 300 K and temperature independent SS below 140 K, indicating the achievable tunneling current steepness with the current device design. Physical modeling and quantum simulations based on the low temperature I-V characteristics were used to analyze the fundamental gate efficiency of the experimental QWTFETs in order to reveal the ultimate intrinsic tunneling steepness of the InGaAs/GaAsSb tunneling junction. The extracted gate efficiency around 55-64% is due to the coupling of the gate capacitance and tunneling junction capacitance and degrades dramatically the attainable SS in the QWTFET. On the other hand, the implied intrinsic tunneling steepness of the InGaA/GaAsSb is around 30 mV/dec, almost identical to previously reported non-abruptness of the conduction/valence band-edge into the bandgap. The result indicates the possibility of achieving SS as low as 38 mV/dec in QWTFETs by improving gate efficiency by up to 78% with proposed optimized parameters based on simulation results. Non-logic TFET-specific circuits are also explored to understand the advantage of TFETs in real-world applications. Due to the superior nonlinearity in the device I-V characteristics and gate-dependent negative-differential-resistance (NDR) under forward bias condition (VDS < 0), experimental and simulation results of QWTFET-based RF detector, oscillator and mixer have demonstrated the potential of QWTFET in these non-logic circuit applications, especially for ultralow standby power applications.en_US
dc.format.extent181 p.en_US
dc.format.mimetypeapplication/pdfen_US
dc.language.isoenen_US
dc.publisherMIT International Center for Air Transportation (ICAT)en_US
dc.subjectElectrical Engineeringen_US
dc.subjectComputer Scienceen_US
dc.subjectTechnologyen_US
dc.subjectInGaAsen_US
dc.subjectGaAsSben_US
dc.titleInGaAs/GaAsSb quantum-well Tunnel-FETs for ultra-low power applicationsen_US
dc.typeThesisen_US
dc.size25.8Mben_US
dc.departmentTechnologyen_US
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